This paper proposes a customized C programmable processor design to implement the speaker localization algorithm that fulfills the challenging requirements placed by the usage context. The high computational complexity combined with low energy requirements to meet the battery constraints of hearing aid devices presents an implementation challenge. However, the binaural speaker localization requires computationally complex audio processing and filtering. The speaker position can be estimated in the frontal azimuth-plane with a probabilistic localization algorithm from the binaural microphone input of the both-eared hearing aid system. State-of-the-art beamforming techniques are able to segregate specific sound sources from the environment, presupposing the position of the speaker. One of the key problems for hearing impaired persons represents the cocktail party scenario, in which a bilateral conversation is surrounded by other speakers and noise sources. Finally, a case study is presented to show the usability of the proposed framework. With the Xtensa Xplorer, different configurations of the Tensilica-based processor architecture are profiled. This framework includes a fixed-point analysis and an automated reference code generation using MATLAB tools. The hearing aid algorithms are implemented in fixedpoint representation to reduce the computational complexity. In order to reduce the exploration time, this paper presents a partly automated design space exploration framework. In this paper, several configurable audio processors are evaluated, using five commonly known acoustic beamforming algorithms. Therefore, a wide variety of design goals must be weighted against each other before a final decision for the architecture can be made. Also, the computational performance and flexibility of an architecture are essential. Various aspects have to be taken into account, like power consumption and silicon area. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.Ĭhoosing a suitable processor architecture for a hearing aid is a difficult task. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Furthermore, an analog front-end and digital audio interfaces are added. The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm². To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises.
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